The invention relates to a system for entering an electronic test pattern into an intergrated circuit. The testing proper should be effected through using only a low number of test data pins. The presenting of selfclocking test data as a serial string would need only a single pin. However, a principal problem then remains to recognize the instant of a transition from normal or functional usage to testing. An advantageous test methodology would, for controlling this transition, need no additional and reserved control pin that would have no usage in the functional mode. Importantly, the circuit should not slip into the test mode during normal usage due to some signal pattern that were then received on the pin that would be used for receiving the test forcing pattern. The signals that were to control the transition should thus be made readily and uniformly distinguishable from the signals that would be presented in normal use to the pin in question.
Various older proposals have been brought forward, inter alia the use of two pins to enter a special test sequence into an in-circuit shift register, which scheme would necessitate more test control pins. An alternative to the present invention is to apply a high voltage to steer the circuit to the test mode. Although this would by itself represent a reliable procedure, the necessity for coping with such a higher voltage would require taking extra measures for good insulation and the like. Generally, it would be advisable for reasons of low cost to use only a single pin for presenting a pattern that would serve to detect an impending start of a test procedure, and to use signals at or near standard voltage levels.
In consequence, amongst other things, it is an object of the present invention to signal an impending transition to a test procedure by using only a single test pin and to apply thereto signals at or near standard voltages.
Now therefore, according to one of its aspects the invention is a system or entering an electronic test pattern into an integrate circuit.
The invention also relates to a method of entering an electronic test pattern into an integrate circuit.